Embodiments of this invention relate generally to a semiconductor device and a method of operating the same, and more particularly to a semiconductor device for suppressing an increase in the peak current of bit lines during a program operation.
FIG. 1 is a block diagram illustrating an increase in the load of bit lines due to high integration of semiconductor devices.
Referring to FIG. 1, a semiconductor device includes a memory cell array 10 for storing data. The memory cell array 10 includes first to kth memory blocks MB1 to MBk. Each of the first to kth memory blocks MB1 to MBk includes a plurality of cell strings (not shown) each comprising a plurality of memory cells for storing data and coupled to respective bit lines BL.
High integration of semiconductor devices leads to an increase in the number of memory blocks in a memory chip and the number of cell strings in each memory block, and thus the load of the bit lines BL may increase. More particularly, an increase in the number of memory blocks MB1 to MBk forming a memory chip causes an increase in the length of each bit line BL. Furthermore, as the number of cell strings increases, the number of bit lines BL increases, and thus a load NBL increases. If a load of the bit lines BL increases as described above, a peak current of the bit lines BL may sharply rise when the semiconductor device is operated, e.g., when the bit lines BL is being precharged. A rise of the peak current is described in detail below with reference to FIG. 2.
FIG. 2 is a graph illustrating peak current due to the increase in the load of bit lines in FIG. 1.
Referring to FIG. 2, the peak current of the bit lines BL is in inverse proportion to the number of bit lines BL to be precharged. That is, the peak current of the bit lines BL is inversely proportional to the number of program data. More particularly, when voltages having different levels are applied to the bit lines BL, electrical charges due to capacitance is generated between adjacent bit lines BL. For example, at the early stage of a program operation, the number of bit lines BL to be precharged is relatively smaller than the number of bit lines BL to be discharged. Accordingly, when a small number of bit lines BL are precharged, a generation of electrical charges due to capacitance increases because a potential difference is generated owing to adjacent and discharged bit lines BL. Thus, a peak current of the precharged bit lines BL also rises. Accordingly, when the program operation is in the first stage, a peak current of the bit lines BL has a maximum value C1. As program operations proceed to later stages, the number of precharged bit lines BL increases because the number of programmed memory cells on which program has been completed is increased. Consequently, a peak current of the bit lines BL decreases as the number of programmed memory cells increases.
As described above, when a program operation is initially performed, a peak current rises because current due to capacitance between the bit lines BL increases. The increase in peak current may cause a power drop called surge power-down, and thus the semiconductor device may be abnormally operated.